Conventionally a VHS system format for a home VTR has been adapted to a control coding system for recording a VHS index search system signal (VISS signal) and a VHS address search system signal (VASS signal) on the tape by changing the duty of control signals to be recorded on a magnetic tape (hereinafter simply referred to as a tape). This system uses two kinds of duty ratios, the 60 (.+-.5) % duty ratio and the 27.5 (.+-.2.5) % duty ratio for the control signals to be recorded, and modulates the control signals according to a predetermined format. Accordingly a reproducer side discriminates between the VISS signal and the VASS signal by discriminating the duty ratios of the control signals.
So, as a way of discriminating the duty ratios of the reproduced control signals, the time that the control signal stays in a high level state is counted based on a predetermined clock and is then compared with a threshold value. Provided that the threshold value is a predetermined constant value, the discriminating operation can not cope with a frequency change of the reproduced control signal. Accordingly, a way of changing the threshold value in response to the frequency of the reproduced control signal has been employed.
FIG. 1 is a block diagram showing an example of conventional pulse duty ratio discrimination circuits for discriminating the duty ratios of the control signals. FIG. 2 is a time chart for explaining the operation of the pulse duty ratio discrimination circuit. 1 denotes a sequencer which generates a counter latch signal 200, a counter reset signal 300 and a sampling pulse 400, based on a reproduced control signal 100 and a reference clock 50. 2 denotes a counter for up-counting the reference clock 50. The counter 2 is reset by the reset signal 300. 3 denotes a latch for latching the count value of the counter 2 at the input timing of the latch signal 200. 4 denotes a divider for dividing in half the (n+1) bit output of the counter 2 and for outputting the divided value as an output A. 5 denotes a magnitude comparator for comparing the magnitude of the output B of the latch 3 with the magnitude of the output A of the divider 4 and for outputting a high level signal into a D-type flip-flop 6 when A&gt;B. 6 denotes the D-type flip-flop for outputting the comparing result of the magnitude comparator 5 as a pulse duty ratio discriminating signal when the comparing result of the magnitude comparator 5 is applied to its data terminal D, and the sampling pulse 400 is applied to its clock terminal CK.
The sequencer 1 generates the counter latch signal 200, the counter reset signal 300 and the sampling pulse 400 from the reproduced control signal 100, as shown in FIG. 2(B). After the counter 2 is reset to 0 at the leading edge of the counter reset signal 300 output from the sequencer 1, as shown in FIG. 2(C), the counter 2 starts to count the reference clock. The count value thus increases, as shown in FIG. 2(A). After that, the counter latch signal 200 is output from the sequencer 1, as shown in FIG. 2(D), the latch 3 latches the count value of the counter 2 at that point, and sends the latched value to the magnitude comparator 5 as an output B (see FIG. 2(F)).
Additionally, the divider 4 successively divides in half the count value of the counter 2 and sends the divided value to the magnitude comparator 5. If the output of the divider 4 is smaller than the output of the latch 3 at the time that the signal 200 has been output, the output of the magnitude comparator 5 becomes a low level at that timing. If the output of the divider 4 becomes larger than the output of the latch 3 before the counter reset pulse 300 is generated in the increase of the count value of the counter 2, the output of the magnitude comparator 5 becomes a high level. If the output of divider 4 remains smaller than the output of the latch 3, the output of the magnitude comparator 5 remains in the low level. The comparing result of the magnitude comparator 5 is transferred to the D-type flip-flop 6 at the output timing of the sampling pulse 400. Therefore, when the duty ratio of the control signal is more than 50%, the Q output of the D-type flip-flop 6 becomes the low level (logic value "0"). When the duty ratio of the control signal is below 50%, the Q output of the D-type flip-flop 6 becomes the high level (logic value "1") and the pulse duty ratio discriminating signal 500 is output, as shown in FIG. 2(H).
Recently, VTRs have exhibited an inclination toward increasing the speeds of fast forwarding/fast rewinding operations for the purpose of improving their operability, so the frequency range of the reproduced control signal 100 is steadily expanding. Accordingly, to cope with this recent inclination the pulse duty ratio discrimination circuit must increase the speed of the reference clock 50 in order to keep the accuracy of the detection in a higher order, which correspondingly increases the bit scale of the counter 2. For instance, if 2% has been set as the accuracy of the detection so as to cope with the high speed of 300 times fast forwarding and/or fast rewinding operation, the frequency of the control signal is given by 30 Hz.times.300 times=9 KHz. Accordingly, in this case the frequency of the reference clock 50 is given by 9 KHz/0.02=450 KHz. To cope with a normal operation control signal 100 with frequency of 30 Hz, the required bit scale of counter 2 is given by 450 KHz/30 Hz=15,000, i.e., 14 bit (= 16384). This requirement increases the circuit scale of the pulse duty ratio discriminating circuit, thereby increasing its cost.
As described above, the conventional pulse duty ratio discrimination circuit, which discriminates the duty ratios of the reproduced control signals by initially counting the time that the control signal stays in a high level state based on a predetermined clock and by then comparing the count value with a threshold value, must use a high speed clock because of the inclination toward expanding the frequency range of control signals. Accordingly, the conventional. pulse duty ratio discrimination circuit has a drawback that necessitates using a large bit scale counter which causes the circuit scale to be enlarged, thereby increasing the cost of the circuit.